Business Wire

Keithley Adds Support for Non-Volatile Memory, Very Low Frequency C-V, and Increased Parallel Testing to Semiconductor Parameter Analyzer

CLEVELAND--(BUSINESS WIRE)--Keithley Instruments, Inc., a world leader in advanced electrical test instruments and systems, has introduced a variety of enhancements for its award-winning Model ...
Semiconductor Engineering

Coping With Parallel Test Site-to-Site Variation

Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each ...
EDN

Handbook explains parallel parametric testing

Keithley Instruments has announced the publication of Parallel Test Technology: The New Paradigm for Parametric Testing, a handbook that covers semiconductor parametric testing. The free, 60-page book ...
EDN

Open architecture supports parallel test

As the transistor geometry shrinks, more transistors are packed on to a single chip, reducing manufacturing cost on a per-transistor basis. The result, however, is more transistors to test; hence, ...
Semiconductor Engineering

Site-To-Site Variation In Parallel Test

From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An ...