IEEE

Hardware Implementation of Systolic Array Architecture using 4:2 Compressor Approximate Multiplier for Image Processing Operations

Abstract: This research presents an innovative FPGA implementation of a $128 \times 128$ convolution systolic array architecture, optimized for image processing applications. The core of this design ...
IEEE

Feature Selection and Classification Optimization of Transformer Oil Odor Data With Recursive Feature Elimination Using Grid Search and Cross-Validation

Abstract: Power transformers are vital for transmitting, distributing, and using energy produced in electrical energy systems. The failure of a distribution transformer can cause significant financial ...