Semiconductor Engineering

A Comprehensive Approach To System-Level ESD

The performance and reliability of an electronics system largely depend on the system’s immunity from an electrostatic discharge (ESD) event. Because the components, custom chips and package come from ...
EDN

ESD target levels: Impacting ESD from components to systems

The Industry Council on ESD Target Levels, since its inception in 2006, has strongly influenced the IC industry’s ESD qualification processes. The industry’s original ESD qualification requirements ...
EDN

Embedded scanning: The next step in ESD detection

The state-of-the-art in robustness design and analysis for ESD (electrostatic discharge) always lags our ability to characterize and qualify a device or system. The ESD Association, IEC, JEDEC, and ...
Business Wire

Apache Introduces PathFinder, the Industry’s First Full-chip ESD Physical Integrity Solution

SAN JOSE, Calif.--(BUSINESS WIRE)--Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced PathFinder™, a ...
Semiconductor Engineering

Shock Value

Chip-Package-System (CPS) ESD simulation enables system-wide ESD robustness validation, a common challenge in automotive and aerospace applications. To enable CPS ESD analysis requires an accurate ...
Electronic Design

Is System-Level ESD Testing Valid for ICs?

Electronic system designs often include transient protection to ensure system robustness for electrostatic discharge (ESD) events. Adding external ESD protection without compromising system I/O speed, ...