Electronic Design

Five Output Ultralow Jitter Clock Distributor with PLL Provides Unique Multichip Output Synchronization Method

Linear Technology Corporation announces the LTC6950, a low phase noise integer-N synthesizer core with an ultralow jitter clock distribution output section. Linear Technology Corporation announces the ...
Just Auto

Continental gets grant for method for protecting network time synchronization against unauthorized changes

Continental has patented a method to protect time synchronization in a network by monitoring messages related to grandmaster clock changes. If a new clock with better parameters is proposed, a virtual ...
Electronic Design

Achieving Sub-ns Synchronization in Ethernet Networks

Time-sensitive networks (TSN) in Ethernet are improving computer-based measurements from sub-microsecond to sub-nanosecond precision. By using message-based protocols that synchronize clocks, it is ...
Redmond Magazine

What To Do About Hyper-V Clock Sync Issues

Fixing out of sync VM clocks may be a bit annoying, but it's 100 percent doable. Here's how. One of the nice things about Hyper-V is that you usually don't have to worry about setting virtual machine ...
EDN

JESD204B Subclasses (part 1): Intro and Deterministic Latency

This insatiable demand for data is what led to the need for JEDEC to introduce the JESD204 standard for a high-speed serial link between data converters and logic devices. The “B” revision of the ...