Semiconductor Engineering

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)

A new technical paper titled “ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions” was published by researchers at Politecnico di Torino and EPFL. Abstract “Modern data-driven ...
Semiconductor Engineering

Freeing Up Near-Memory Capacity For Cache Using Compression Techniques In A Flat Hybrid-Memory Architecture

A technical paper titled “HMComp: Extending Near-Memory Capacity using Compression in Hybrid Memory” was published by researchers at Chalmers University of Technology and ZeroPoint Technologies.

New memory architecture targets AI inference bottlenecks

Lightbits Labs Ltd. today is introducing a new architecture aimed at addressing one of the most stubborn bottlenecks in large-scale artificial intelligence inference: the growing mismatch between the ...